1. Field of the Invention
The present invention relates to a semiconductor apparatus having a CPU and an internal resource and having an external resource connected thereto. The present invention also relates to a read access method, in such a semiconductor apparatus, for a CPU to an internal resource and an external resource.
2. Description of Related Art
FIG. 1 shows a circuit diagram of an essential portion of an example of an information processing system in the related art. A semiconductor apparatus 1 includes a CPU 2. An internal address bus 3 acts as an internal address transfer path. An internal data bus 4 acts as an internal data transfer path.
The CPU 2 accesses an internal resource 5. A bus control portion 6 controls use of the internal data bus 4. A buffer 7 is provided for an external address bus 12.
Three-state buffers 8 and 9 are provided for an external data bus 13. Three-state buffers 10 and 11 are provided between the internal data bus 4 and the internal resource 5.
The external address bus 12 acts as an external address transfer path. The external data bus 13 acts as an external data transfer path. The CPU also accesses an external resource 14. Three-state buffers 15 and 16 are provided between the external data bus 13 and the external resource 14.
The CPU 2 outputs a read/write control signal via a read/write control signal line 17. The read/write control signal determines whether each of the three-state buffers 8, 9, 10, 11, 15 and 16 is in an active state or a inactive state.
In this information processing system, when the CPU 2 performs a read access to the internal resource or the external resource, an address is supplied from the CPU 2 to the internal address bus 3. This address is decoded by the bus control portion 6. Thereby, when a read access is indicated by the read/write control signal which is input to the read/write control line 17 from the CPU 2, whether the CPU 2 performs the read access to the internal resource 5 or the external resource 14 is determined.
When it is determined that the CPU 2 performs read access to the internal resource 5, by the bus control portion 6, three-state buffers 9 and 16 are controlled to be in the inactive state and the output ends of the three-state buffers 9 and 16 have high impedances. Further, the three-state buffer 11 is controlled to be in the active state and the CPU 2 receives data from the internal resource 5.
When it is determined that the CPU 2 performs read access to the external resource 14, by the bus control portion 6, the three-state buffer 11 is controlled to be in the inactive state and the output end of the three-state buffer 11 has a high impedance. Further, the three-state buffers 9 and 16 are controlled to be in the active state and the CPU 6 receives data from the external resource 14.
Thus, in the semiconductor apparatus 1, when the CPU 2 performs read access to the internal resource 5 or the external resource 14, the bus control portion 6 decodes the address input to the internal address bus 3 from the CPU 2. Then, based on the decoded result, the internal resource 5 is connected to the internal data bus 4 via the three-state buffer 11, or the external resource 14 is connected to the internal bus 4 via the three-state buffer 16, external data bus 13 and three-state buffer 9. Thereby, it is not possible to perform a high-speed read access by the CPU 2 to the internal resource 5 or the external resource 14. Further, until the address is decoded, the three-state buffers 9 and 11 are in the active state and are in the inactive state. Accordingly, power consumption is large.